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March 2008 Rev 6 1/841STM32F103x6STM32F103x8 STM32F103xBPerformance line, ARM-based 32-bit MCU with Flash, USB, CAN,seven 16-bit timers, two ADCs a

Description STM32F103xx10/84 Clocks and startupSystem clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected

STM32F103xx Description 11/84Voltage regulatorThe regulator has three operation modes: main (MR), low power (LPR) and power down.● MR is used in the n

Description STM32F103xx12/84 RTC (real-time clock) and backup registersThe RTC and the backup registers are supplied through a switch that takes pow

STM32F103xx Description 13/84Advanced control timer (TIM1)The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels

Description STM32F103xx14/84 Universal serial bus (USB)The STM32F103xx performance line embeds a USB device peripheral compatible with the USB Full-

STM32F103xx Description 15/84Figure 1. STM32F103xx performance line block diagram 1. TA = –40 °C to +105 °C (junction temperature up to 125 °C).2. AF

Description STM32F103xx16/84 Figure 2. Clock tree1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achiev

STM32F103xx Pin descriptions 17/843 Pin descriptionsFigure 3. STM32F103xx performance line BGA100 balloutAI16001bPE10PC14-OSC32_INPC5PA5PC3PB4PE15PB2P

Pin descriptions STM32F103xx18/84 Figure 4. STM32F103xx performance line LQFP100 pinout1009998979695949392919089888786858483828180797877761234567891

STM32F103xx Pin descriptions 19/84Figure 5. STM32F103xx performance line LQFP64 pinoutFigure 6. STM32F103xx performance line LQFP48 pinout64 63 62 61

Contents STM32F103xx2/84 Contents1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Pin descriptions STM32F103xx20/84 Figure 7. STM32F103xx VFQFPN36 pinoutVSS_3BOOT0PB7PB6PB5PB4PB3PA15PA1436 35 34 33 32 31 30 29 28VDD_3127VDD_2OSC_I

STM32F103xx Pin descriptions 21/84 Table 3. Pin definitionsPins Pin nameType(1)I / O Level(2)Main function(3) (after reset)Alternate functions

Pin descriptions STM32F103xx22/84 K2 13 17 26 10 PA3 I/O PA3USART2_RX(7)/ADC12_IN3/TIM2_CH4(7)E4 - 18 27 - VSS_4SVSS_4F4 - 19 28 - VDD_4SVDD_4G3 14

STM32F103xx Pin descriptions 23/84F7 24 32 50 19 VDD_1SVDD_1K8 25 33 51 - PB12 I/O FT PB12SPI2_NSS(6)/I2C2_SMBAl(6)/USART3_CK(6)(7)/TIM1_BKIN(7)J8 26

Pin descriptions STM32F103xx24/84 B1033457124 PA12 I/OFT PA12USART1_RTS/ CANTX(7) /TIM1_ETR(7) / USBDPA10 34 46 72 25 PA13/JTMS/SWDIO I/O FT JTMS/SW

STM32F103xx Pin descriptions 25/84A4 46 62 96 - PB9 I/O FT PB9 TIM4_CH4(6) (7)I2C1_SDA / CANTXD4 - - 97 - PE0 I/O FT PE0 TIM4_ETR(6)C4 - - 98 - PE1 I/

Memory mapping STM32F103xx26/84 4 Memory mappingThe memory map is shown in Figure 8.Figure 8. Memory mapreserved1 Kbit0x4000 00000x4000 04000x4000 0

STM32F103xx Electrical characteristics 27/845 Electrical characteristics5.1 Test conditionsUnless otherwise specified, all voltages are referred to VS

Electrical characteristics STM32F103xx28/84 5.1.6 Power supply schemeFigure 11. Power supply schemeFigure 9. Pin loading conditions Figure

STM32F103xx Electrical characteristics 29/845.1.7 Current consumption measurementFigure 12. Current consumption measurement schemeai14126VBATVDDVDDAID

STM32F103xx Contents 3/845.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575.3.15 Communicat

Electrical characteristics STM32F103xx30/84 5.2 Absolute maximum ratingsStresses above the absolute maximum ratings listed in Table 4: Voltage char

STM32F103xx Electrical characteristics 31/84 5.3 Operating conditions5.3.1 General operating conditions 5.3.2 Operating conditions at

Electrical characteristics STM32F103xx32/84 5.3.3 Embedded reset and power control block characteristicsThe parameters given in Tabl e 9 are derive

STM32F103xx Electrical characteristics 33/845.3.4 Embedded reference voltageThe parameters given in Tabl e 1 0 are derived from tests performed under

Electrical characteristics STM32F103xx34/84 Table 11. Maximum current consumption in Run mode, code with data processingrunning fr

STM32F103xx Electrical characteristics 35/84Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -code with data processing

Electrical characteristics STM32F103xx36/84 Table 13. Maximum current consumption in Sleep mode, code running from Flash or RAMSym

STM32F103xx Electrical characteristics 37/84Figure 15. Current consumption in Stop mode with regulator in Run mode versus temperature atVDD = 3.3 V an

Electrical characteristics STM32F103xx38/84 Figure 17. Current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 VTypical curren

STM32F103xx Electrical characteristics 39/84 Table 15. Typical current consumption in Run mode, code with data processingrunning from FlashSym

List of tables STM32F103xx4/84 List of tablesTable 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrical characteristics STM32F103xx40/84 Table 16. Typical current consumption in Sleep mode, code with data processingcode running from

STM32F103xx Electrical characteristics 41/84 On-chip peripheral current consumptionThe current consumption of the on-chip peripherals is given

Electrical characteristics STM32F103xx42/84 5.3.6 External clock source characteristicsHigh-speed external user clock The characteristics g

STM32F103xx Electrical characteristics 43/84 Table 19. High-speed external (HSE) user clock characteristicsSymbol Parameter Conditions Min Typ

Electrical characteristics STM32F103xx44/84 Low-speed external user clock The characteristics given in Ta bl e 2 0 result from tests performed using

STM32F103xx Electrical characteristics 45/84Figure 19. Low-speed external clock source AC timing diagramai14144bOSC32_INEXTERNALSTM32F103xxCLOCK SOURC

Electrical characteristics STM32F103xx46/84 High-speed external clockThe high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/

STM32F103xx Electrical characteristics 47/84Low-speed external clockThe low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceram

Electrical characteristics STM32F103xx48/84 5.3.7 Internal clock source characteristicsThe parameters given in Tabl e 2 3 are derived from tests pe

STM32F103xx Electrical characteristics 49/84Wakeup time from low-power modeThe wakeup times given in Tab le 2 5 is measured on a wakeup phase with a

STM32F103xx List of tables 5/84Table 45. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrical characteristics STM32F103xx50/84 5.3.9 Memory characteristicsFlash memoryThe characteristics are given at TA = −40 to 105 °C unless other

STM32F103xx Electrical characteristics 51/845.3.10 EMC characteristicsSusceptibility tests are performed on a sample basis during device characterizat

Electrical characteristics STM32F103xx52/84 Electromagnetic Interference (EMI)The electromagnetic field emitted by the device are monitored while a

STM32F103xx Electrical characteristics 53/845.3.12 I/O port characteristicsGeneral input/output characteristicsUnless otherwise specified, the paramet

Electrical characteristics STM32F103xx54/84 Output driving currentThe GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and si

STM32F103xx Electrical characteristics 55/84Input/output AC characteristicsThe definition and values of input/output AC characteristics are given in F

Electrical characteristics STM32F103xx56/84 Figure 22. I/O AC characteristics definition 5.3.13 NRST pin characteristicsThe NRST pin input driver us

STM32F103xx Electrical characteristics 57/84Figure 23. Recommended NRST pin protection 2. The reset network protects the device against parasitic rese

Electrical characteristics STM32F103xx58/84 5.3.15 Communications interfacesI2C interface characteristicsUnless otherwise specified, the parameters

STM32F103xx Electrical characteristics 59/84Figure 24. I2C bus AC waveforms and measurement circuit1.Measurement points are done at CMOS levels: 0.3VD

List of figures STM32F103xx6/84 List of figuresFigure 1. STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . .

Electrical characteristics STM32F103xx60/84 SPI interface characteristicsUnless otherwise specified, the parameters given in Ta bl e 40 are derived

STM32F103xx Electrical characteristics 61/84Figure 25. SPI timing diagram - slave mode and CPHA = 0Figure 26. SPI timing diagram - slave mode and CPHA

Electrical characteristics STM32F103xx62/84 Figure 27. SPI timing diagram - master mode(1)1. Measurement points are done at CMOS levels: 0.3VDD and

STM32F103xx Electrical characteristics 63/84Figure 28. USB timings: definition of data signal rise and fall time 5.3.16 CAN (controller area n

Electrical characteristics STM32F103xx64/84 5.3.17 12-bit ADC characteristicsUnless otherwise specified, the parameters given in Ta bl e 44 are der

STM32F103xx Electrical characteristics 65/84Equation 1: RAIN max formula:The formula above (Equation 1) is used to determine the maximum external impe

Electrical characteristics STM32F103xx66/84 Figure 29. ADC accuracy characteristicsTable 47. ADC accuracy(1) (2)1. ADC DC accuracy values a

STM32F103xx Electrical characteristics 67/84Figure 30. Typical connection diagram using the ADC1. Refer to Ta bl e 4 4 for the values of CAIN, RAIN, R

Electrical characteristics STM32F103xx68/84 Figure 32. Power supply and reference decoupling (VREF+ connected to VDDA)1. VREF+ and VREF– inputs are

STM32F103xx Package characteristics 69/846 Package characteristics6.1 Package mechanical dataIn order to meet environmental requirements, ST offers t

STM32F103xx Introduction 7/841 IntroductionThis datasheet provides the STM32F103xx performance line ordering information and mechanical device charact

Package characteristics STM32F103xx70/84 1. Drawing is not to scale.2. The back-side pad is not internally connected to the VSS or VDD powe

STM32F103xx Package characteristics 71/84Figure 35. LFBGA100 - low profile fine pitch ball grid array package outline1. Drawing is not to scale.

Package characteristics STM32F103xx72/84 Figure 36. Recommended PCB design rules (0.80/0.75 mm pitch BGA)DpadDsmDpad 0.37 mmDsm0.52 mm typ. (depends

STM32F103xx Package characteristics 73/84 Figure 37. LQFP100, 100-pin low-profile quad flat package outline(1)Figure 38. Recommended

Package characteristics STM32F103xx74/84 Figure 39. LQFP64, 64-pin low-profile quad flat package outline(1)Figure 40. Recommended

STM32F103xx Package characteristics 75/84 Figure 41. LQFP48, 48-pin low-profile quad flatpackage outline(1)Figure 42. Recommended foo

Package characteristics STM32F103xx76/84 6.2 Thermal characteristicsThe maximum chip junction temperature (TJmax) must never exceed the values given

STM32F103xx Package characteristics 77/846.2.2 Selecting the product temperature rangeWhen ordering the microcontroller, the temperature range is spec

Package characteristics STM32F103xx78/84 Using the values obtained in Ta bl e 5 4 TJmax is calculated as follows:– For LQFP100, 46 °C/W TJmax = 115

STM32F103xx Ordering information scheme 79/847 Ordering information scheme For a list of available options (speed, package, etc.) or for furt

Description STM32F103xx8/84 2.1 Device overview Table 2. Device features and peripheral counts (STM32F103xx performance line)PeripheralSTM32

Revision history STM32F103xx80/84 8 Revision history Table 56. Document revision historyDate Revision Changes01-jun-2007 1 Initial release.2

STM32F103xx Revision history 81/8418-Oct-2007 3STM32F103CBT6, STM32F103T6 and STM32F103T8 root part numbers added (see Table 2: Device features and pe

Revision history STM32F103xx82/84 22-Nov-2007 4Document status promoted from preliminary data to datasheet.The STM32F103xx is USB certified. Small t

STM32F103xx Revision history 83/8414-Mar-2008 5Figure 2: Clock tree on page 16 added.Maximum TJ value given in Table 6: Thermal characteristics on pag

STM32F103xx84/84 Please Read Carefully:Information in this document is provided solely in connection with ST products. STMicroelectronics

STM32F103xx Description 9/842.2 OverviewARM® CortexTM-M3 core with embedded Flash and SRAMThe ARM Cortex-M3 processor is the latest generation of ARM